Abstract:
Future two dimensional materials offer great promise for nanoelectronics as conventional semiconductor advancements are highly limited in terms of power and performance dissipation for new technology nodes. Since great carrier mobility is necessary for low voltage device operations and high performance, greatly scaled field-effect transistors with minimal short-channel effects are made possible by the atomic thickness of 2D materials. Interface engineering is essential for improving the performance of 2D layered semiconductor devices as well as conventional electronics. Defect free nature of Graphene, uniformity, inert nature and being very thin reduce the amount of interfacial interaction and provide well defined interfaces with MoS2. The work function of graphene and MoS2 has a very small difference which makes the charge carriers injection easy. Using Graphene as the source and drain electrodes results in an increase in the mobility. MoS2 based field-effect transistors (FETs) exhibit high threshold voltage hysteresis (VTH) due to interface traps present at their gate interfaces. In order to address the problem, the VTH of MoS2 FETs is dramatically decreased by adding a passivation layer made of 3-aminopropyltriethoxysilane (APTES) at the gate interface of MoS2/SiO2 due to the passivation of the interface traps. Verification by contact angle spectrometry confirms the successful deposition of self-assembled monolayers (SAMs). Two-dimensional graphene and MoS2 are produced via mechanical exfoliation and transferred using a dry transfer process with Polydimethylsiloxane (PDMS), while SAMs are created using the immersion method with PDMS. The layer count of two-dimensional materials is determined through Raman spectroscopy by analyzing the frequency difference between peaks. The electrical performance of the FET demonstrates an improvement in the mobility of the transistors, up to 103 cm2/Vs, when employing graphene electrodes. The mobility increases to 135 cm2/Vs and the threshold voltage decreases via APTES passivation. Both devices exhibit a modest on/off ratio. The insertion of an interfacial layer between the semiconductor and electrode results in a significant reduction of contact resistance. The use of n-type graphene as electrodes will lead to higher mobility. The channel of the field effect transistor (FET) can be protected from contamination through the utilization of hydrophobic self-assembled monolayers, which will passivate the channel from the top.
